In the common tunneling solar cell, during the manufacturing process, a silicon oxide layer is generally grown at a side of the silicon wafer as a tunneling layer. However, the silicon oxide layer cannot have good passivation characteristics, and therefore a high-temperature annealing process needs to be performed to increase passivation quality.
The high-temperature annealing process is generally performed in a furnace. In the high temperature state, the silicon oxide layer grows such that the thickness thereof exceeds 2 nm. As a result, the carriers in the silicon wafer cannot be freely transported via the tunneling mechanism. Therefore, before the annealing process is performed, a doped amorphous silicon layer can be formed on the silicon oxide layer to prevent the exceeding growth of the silicon oxide layer. However, during the annealing process, the doped amorphous silicon layer is changed into a doped polysilicon layer, and holes passing through the doped amorphous silicon layer and the silicon oxide layer are generated at the same time. The generation of the holes significantly reduces the passivation capability of the silicon oxide layer. Moreover, since the band gap of polysilicon and the band gap of single-crystal silicon are both close to 1.1 eV, the surface defects of the silicon wafer cannot be effectively passivated, and therefore the open-circuit voltage (Voc) of the solar cell cannot be effectively improved.